Cascadable current-mode regulator
US7061215B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Mar 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1584
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A cascadable power regulator including a programmable delay unit and PWM control logic. The programmable delay unit initiates a delay period in response to a digital input signal and asserts a digital output signal upon expiration of the delay period. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. Thus, the number of phases is not limited, the physical separation between the regulators is not limited, and the switching frequency is not as limited. There is no clock signal from a separate controller so that the controller is a relatively simple, low-cost device. Since there is no clock, a unique self-oscillating system is achieved using the cascadable regulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.