Methods and apparatus for improving impedance tolerance of on-die termination elements
US7061266B2 · kind B2 · utility
4Cited by
3References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Oct 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An impedance calibration circuit in an integrated circuit includes a master current source to force a master current to flow through a first load that is external to the integrated circuit. The master current source includes a stabilized current source to provide a first part of the master current and a first supplementary current source to provide a supplementary part of the master current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.