Field programmable gate array
US7061275B2 · kind B2 · utility
3Cited by
101References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2005 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Oct 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that can perform combinatorial logic. The logic head can further be fractured into two independent logical units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.