High frequency divider state correction circuit with data path correction
US7061284B2 · kind B2 · utility
3Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | May 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/58
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip flop is coupled to the output of the third flip flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.