Low supply voltage analog multiplier
US7061300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2001 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Feb 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.