Addressing technique for an active backplane device
US7061463B2 · kind B2 · utility
4Cited by
7References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2002 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Feb 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0205
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An active semiconductor backplane for a matrix liquid crystal display comprises a plurality of mutually exclusive sets of electrically-addressable elements defining a pixel array. Scanning circuitry addresses the sets one at a time. Set selection circuitry addresses more than one of the plurality of sets simultaneously. Preferably, the sets are simultaneously addressable rows for fast blanking. Single pass and two-pass schemes for writing and re-writing the array are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.