Master slave frame lock method
US7062005B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2002 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Aug 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a system for synchronising slave and master timing, comprising a phase adjust circuit for receiving and delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to the slave timing, and a master phase detector and lock circuit for comparing relative phases of the master and slave timing and in response generating and applying delay adjust signals to the phase adjust circuit at a dynamically adjusted rate which is related to the relative phase in order to synchronise the slave and master timing and is thereafter reduced to a minimum rate required to maintain synchronisation of the slave and master timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.