Circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method
US7062525B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Jul 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method. In one embodiment, the circuit includes: (1) left-shift circuitry for aligning a fractional part of the floating-point result with a most significant bit of the datapath and irrespective of a width of the fractional part to yield a shifted fractional part and (2) rounding circuitry, coupled to the shift circuitry, that rounds the shifted fractional part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.