Microprocessor with rounding multiply instructions
US7062526B1 · kind B1 · utility
80Cited by
10References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Aug 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is combined with a least significant product of a second pair of elements, the combined product is rounded, and the final result is stored in a destination. Rounding is performed by adding a rounding value to form an intermediate result, and then shifting the intermediate result right. A combined result is rounded to a fixed length shorter than the combined product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.