Flexible processing hardware architecture
US7062578B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2001 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Oct 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T5/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.