Methods and apparatus for hardware normalization and denormalization
US7062657B2 · kind B2 · utility
10Cited by
17References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 16, 2001 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Jun 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/122
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques are applied to data prior to cryptography processing. Context circuitry tracks the shift amount used for normalization. After cryptography processing, the processed data is denormalized using the shift amount tracked by the context circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.