Memory implementation for handling integrated circuit fabrication faults
US7062695B2 · kind B2 · utility
3Cited by
4References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 23, 2003 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Aug 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.