Efficient parity operations
US7062702B2 · kind B2 · utility
2Cited by
34References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2001 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Feb 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.