Floorplan evaluation, global routing, and buffer insertion for integrated circuits
US7062743B2 · kind B2 · utility
25Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2003 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Apr 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3947
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for evaluating a floorplan and for defining a global buffered routing for an integrated circuit including constructing a graphical representation of the integrated circuit floorplan, including wire capacity and buffer capacity; formulating an integer linear program from said graphical representation; finding a solution to said integer linear program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.