Barrier layer stack to prevent Ti diffusion
US7064056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Nov 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved barrier layer stack and method for forming the same for preserving an aluminum alloy interconnect resistivity, the method comprising providing a semiconductor process wafer comprising an exposed conductive region; forming a first barrier layer comprising a barrier layer stack over the exposed conductive region comprising one of a TiN or Ti layer in contact with the conductive region; forming at least one additional barrier layer comprising the barrier layer stack to form an alternating sequence of TiN and Ti layers; forming an uppermost barrier layer of TiN comprising the barrier layer stack; forming an overlying aluminum alloy region in contact with the uppermost barrier layer; and, subjecting the semiconductor process wafer to at least one process comprising a temperature of greater than temperatures greater than about 350° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.