DMOS-transistor with lateral dopant gradient in drift region and method of producing the same
US7064385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Dec 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A DMOS-transistor has a trench bordered by a drift region including two doped wall regions and a doped floor region extending along the walls and the floor of the trench. The laterally extending floor region has a dopant concentration gradient in the lateral direction. For example, the floor region includes at least two differently-doped floor portions successively in the lateral direction. This dopant gradient in the floor region is formed by carrying out at least one dopant implantation from above through the trench using at least one mask to expose a first area while covering a second area of the floor region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.