PWM buck regulator with LDO standby mode
US7064531B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2005 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A voltage regulator is disclosed having a PWM portion and an LDO portion on a single chip. The PWM portion switches a large MOS transistor (or synchronous MOS transistors) at a high frequency to supply medium and high currents (e.g., 600 mA) to a load. During a standby mode, the regulator switches to an LDO mode and disables the PWM portion. The LDO mode controls a very small MOS series transistor to supply the standby mode current. Since the gate of the series MOS transistor is small, only a small variation in gate charge is needed to adequately control the conductance of the series transistor during the standby mode. Therefore, much less control current is used by the LDO than if the LDO used a series transistor of the same size as the switching transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.