Differential input receiver
US7064595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Dec 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The differential input receiver provides constant symmetrical hysteresis over a wide input signal range. The differential input receiver includes a pair of complementary differential comparators having common input terminals, a pair of series connected complementary current mirrors each having source terminals driven by the output terminals of the corresponding differential comparator, a pair of transistors connected in series across each differential pair transistor in each differential comparator to form a potential divider across it, and a pair of series connected inverting buffers connected to a common output of the differential comparators to provide the final output. The individual buffer outputs are fed back to the control terminals of the series connected transistors in a manner that provides positive feedback thereby providing equal rise-time, fall-delay and transition times in the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.