Radio frequency CMOS buffer circuit and method
US7064598B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2004 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Mar 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018571
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer (40) includes a capacitor (42) having a first terminal for receiving an input signal, and a second terminal; a first transistor (44) having a first current electrode for receiving a first power supply voltage, a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for providing an output signal of the buffer (40); and a second transistor (45) having a first current electrode coupled to the second current electrode of the first transistor (44), a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for receiving a second power supply voltage. A capacitance of the capacitor (42) is chosen to reduce a peak-to-peak voltage swing of the input signal such that a peak-to-peak voltage swing at the control electrodes of the first (44) and second (45) transistors is less than or equal to a difference between the first and second power supply voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.