PLL with swappable tuning loops
US7064618B2 · kind B2 · utility
0Cited by
2References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a switch capacitor circuit to generate a first output capacitance based on a control signal, a main loop circuit to generate an output signal based on the control signal, and an oscillating circuit to generate an oscillating signal, a frequency of the oscillating signal based at least on the first output capacitance and the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.