Jitter reduction
US7065168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1999 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Aug 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Decoders process a digital input word to derive thermometer-coded signals for controlling one cell of an array of cells, commencing operation at the rising edge of a first clock signal. Each cell has a first latch clocked by a second clock signal, delayed by a preselected delay time Δ1 relative to the first clock signal, and a second, transparent latch clocked by a third clock signal whose rising edge coincides with the rising edge of the first clock signal and whose falling edge coincides with the rising edge of the second clock signal. The rising edge of the third clock signal is not affected by jitter associated with a delay element used to delay the first clock signal by Δ1. The falling edge is affected by such jitter, but is prevented from feeding through to final outputs because the second latch is non-transparent at that falling edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.