System and method for implementing a counter
US7065607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Dec 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In one embodiment, the counter is implemented in m+n bits. The bits of the counter are grouped into a binary portion of the counter of m bits and a unary portion of the counter of n bits. In order to increment the counter, the unary portion of the counter is incremented first. When the unary portion of the counter reaches a specific value, the binary portion of the counter is incremented. This limits 1 to 0 bit transitions and allows a large range of unique values to be read from the counter. In another embodiment, two unary counters are formed, which dynamically change in size as the counter is incremented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.