Address translation logic for use in a GPS receiver
US7065629B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2002 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | May 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S19/37
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The address translation logic of the present invention is incorporated in a global positioning system (GPS) receiver and operates to group data in memory based on translating the address from a direct memory access controller. The data includes post-correlated samples of the correlation of a signal with a generated frequency and a generated code having a plurality of time offsets. In general, the address translation logic organizes the data such that each element of the data associated with particular ones of the plurality of time offsets are grouped together in order to improve the efficiency of performing a fast Fourier transform of the data. In addition, the address translation logic allows the transfer of data from correlation circuitry to memory, from the memory to an FFT module, and from the FFT module to the memory using standard DMA controllers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.