Hardware loops and pipeline system using advanced generation of loop parameters
US7065636B2 · kind B2 · utility
2Cited by
7References
29Claims
0Family size
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Key dates
| Filing date | Dec 20, 2000 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.