Method and system for providing high-speed forward error correction for multi-stream data
US7065696B1 · kind B1 · utility
15Cited by
16References
23Claims
0Family size
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Key dates
| Filing date | Apr 11, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | May 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2936
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for providing a high-speed implementation for multi-stream forward error correction (FEC) is provided. According to one exemplary aspect, the system is able to provide block-based multi-stream FEC that reduces the power consumption when compared with conventional symbol-based FEC. The system provides a pipeline architecture for multi-stream FEC so that modules in the system are able to respectively process blocks of data from different channels or data streams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.