Systems and methods of partitioning data to facilitate error correction
US7065697B2 · kind B2 · utility
4Cited by
16References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 29, 2003 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The bits in the adjacent bit pair domain are processed by an error correction unit sequentially or in parallel, and then recombined to be written into memory or transmitted to a requestor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.