Optimal simultaneous design and floorplanning of integrated circuit
US7065727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2001 |
| Grant date | Jun 20, 2006 |
| Priority date | — |
| Expiry date | Nov 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described for optimal simultaneous design and floorplanning of integrated circuits. The method is based on formulating the problem as a geometric program, which then can be solved numerically with great efficiency. Prior work discloses the design of many different analog circuit cells such as operational amplifiers, spiral inductors, and LC oscillators which can be cast as geometric programs. The present disclosure adds to this layout floorplanning constraints in posynomial form that can be mixed with design constraints for different analog circuits. This allows the simultaneous design and floorplanning of numerous analog circuits using geometric programming. Thus, the design and floorplanning can be performed optimally in a single step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.