Method of manufacturing dielectric isolated silicon structure
US7067387B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2003 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Oct 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/762
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating dielectric isolated silicon islands or regions is described in this invention. A hard composite mask of pad oxide and silicon nitride is first patterned on a silicon substrate and trenches of required dimensions are etched into silicon. After forming an oxide liner on trench surfaces, boron ions are implanted in areas around the trenches such that heavily doped p+ regions are formed. The oxide liner is anisotropically etched with a reactive ion etching process such that only the silicon surface at trench bottom is exposed, leaving the oxide liner on trench walls. Epitaxial silicon is then deposited selectively on exposed single crystal silicon surface so as to fill the trenches. After removing the hard mask, trenches are masked with photo-resist pattern and the wafer is anodically etched in an aqueous bath of HF to form a buried porous silicon layer under and around the trenches. After removing the mask, the porous silicon is then oxidized. Discrete silicon regions, electrically isolated by silicon dioxide, are then formed after removing the top oxide film on the epitaxial silicon surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.