Method and apparatus for using capacitively coupled communication within stacks of laminated chips
US7067910B2 · kind B2 · utility
21Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Oct 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a technique for assembling semiconductor chips. First, multiple semiconductor chips are permanently laminated together into a plurality of laminated chip assemblies, wherein the semiconductor chips within the laminated chip assembly communicate with each other through electrically conductive connections. Next, laminated chip assemblies are stacked together to form a stack of semiconductor chips without permanently bonding the laminated chip assemblies together, wherein the laminated chip assemblies communicate with each other using capacitive coupling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.