Digitally programmable I/Q phase offset compensation
US7068089B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | May 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/265
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective application of bias voltages to the MOS varactors may be employed to selectively delay one pair of differential signals with respect to another pair of differential signals so as to change the relative phases of the signals. A logic circuit may be used to control the application of bias voltage to the MOS varactors so that signal phases may be adjusted in a manner that is predictable and programmable. These methods may be implemented to compensate for phase offsets between in-phase and quadrature signals of a local oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.