Phase error cancellation
US7068110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Jun 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A noise cancellation signal is generated for a fractional-N phase-locked loop by supplying a divide value to a first delta sigma modulator and generating a divide control signal in a first delta sigma modulator to control a divide value of a feedback divider in the phase-locked loop. The first delta sigma modulator integrates an error term indicative of a difference between a value of the generated divide control signal and the divide value supplied to the first delta sigma modulator. A phase error cancellation signal is generated by quantizing the integrated error term using a second delta sigma modulator. The error term can be used by the second delta sigma modulator while quantizing the integrated error term, thereby limiting the low pass filter effects of the second delta sigma modulator in the cancellation signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.