Accurate sampling technique for ADC
US7068195B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2005 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time interleaved ADC system includes a delay circuit that has a dynamically adjusted speed to achieve uniformly spaced sampling intervals. The adjustment control circuit monitors the sampling pulses associated with sampling time instant for each ADC, and provides one or more control signals to the delay circuit. In one example, the adjustment control circuit employs a phase detector circuit, an integrator circuit, and a dynamic biasing circuit. In this example, the phase detector circuit evaluates the sampling pulses to generate control signals for the integrator circuit, which generates signals that are utilized by the dynamic biasing circuit to adjust the delays associated with the delay circuit. The relative positions of the sampling pulses are controlled by adjusting the delay in the delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.