Semiconductor integrated circuit with noise reduction circuit
US7068548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Dec 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potential supplying circuit, formed on the substrate, having an input node to receive an input potential from the second node and an output node to supply a substrate potential to the substrate, the substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through the input node, and configured to generate at the output node an output potential following the input potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.