Data decision circuit using clock signal which has phase optimized with respect to phase of input data signal
US7068747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2001 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Aug 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a data decision circuit: a clock generation unit generates a clock signal based on a phase difference signal so that the clock signal has an optimum phase with respect to a phase of an input data signal; a data determination unit determines data values carried by the input data signal, by using the clock signal; a phase-difference detection unit detects a rising-side phase difference and a falling-side phase difference, where the rising-side phase difference is a phase difference between a rising of the input data signal and a next transition in the clock signal, and the falling-side phase difference is a phase difference between the transition and a next falling of the input data signal; and a phase-difference-signal generation unit generates the phase difference signal so as to represent a difference between the rising-side phase difference and the falling-side phase difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.