Method and arrangement for signal loop test
US7069165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2004 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Sep 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M3/306
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The invention refers to single-ended test of a loop with the aid of a transceiver, wherein an input impedance (Zin(ƒ)) of the loop is generated. The transceiver has a digital part, a codec and an analog part and is connected to the loop. With the aid of a transmitted and a reflected broadband signal (vin, vout) an echo transfer function Hecho(ƒ)=V(f)out/Vin(f) is generated, which also can be expressed asHere Zh0(ƒ), Zhyb(ƒ) and H∞(ƒ) are model values for the transceiver. In a calibration process a test transceiver, with the same type of hardware as the transceiver, is connected to known impedances, replacing the loop. Hecho(ƒ)=V(f)out/Vin(f) is generated for the known impedances and the model values are generated and are stored in a memory in the transceiver. The stored model values are then used when the input impedance (Zin(ƒ)) for the loop is generated after a measurement of the broadband signal (Vin, vout) is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.