Method and apparatus for avoiding race condition with edge-triggered interrupts
US7069367B2 · kind B2 · utility
4Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Sep 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a system for avoiding race conditions when using edge-triggered interrupts includes a processor that asserts an interrupt pending signal in response to the receipt of an edge-triggered interrupt. A power management device receives the interrupt pending signal. If the processor is in a low power state when it asserts the interrupt pending signal, then the power management device causes the processor to enter a high power state to allow the processor to service the pending interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.