Decode and dispatch of multi-issue and multiple width instructions
US7069420B1 · kind B1 · utility
2Cited by
9References
18Claims
0Family size
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Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Jul 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single register and determines the number and size of instructions while the instructions are in the register. Each of the plurality of instructions is then simultaneously presented to the decoder. The decoder then decodes a first of the plurality of instructions and determines whether any additional instructions are present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.