Parallel data interface and method for high-speed timing adjustment
US7069458B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2002 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Mar 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0996
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A parallel data interface and method is provided herein, which adjusts a timing relationship of a clock signal to not only minimize clock skew, but to also compensate for noise components that may affect one or more paths of a parallel data bus. In some embodiments, the parallel data interface includes a first phase generator coupled to generate a first plurality of time delay pulses, and a first phase selector adapted to select one of the first plurality of time delay pulses to adjust the timing of a clock signal to sample each and every one of the plurality of data signals between minimum setup and hold time thresholds. In some embodiments, the parallel data interface includes a second phase generator coupled to generate a second plurality of time delay pulses, and a second phase selector adapted to select one of the second plurality of time delay pulses to adjust the timing of the clock signal to output the plurality of data signals from the data interface at least an amount of time (i.e., an access time) after the adjusted clock transition is output from the data interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.