System and method for intelligent trap analysis
US7069470B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Feb 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for intelligent trap analysis for debugging software on a computer system. Instead of dumping only a register context snapshot or all of memory to a file, a trap handler determines a likely cause of a trapped instruction and selects relevant memory addresses for copying to a file. The relevant memory addresses and their contents are preserved for later analysis. The trap handler may step back through the process instruction list searching for relevant memory addresses referenced by the instructions preceding the trapped instruction. The module may undo the effect of instructions as it steps back through the instruction list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.