Data recovery circuit for minimizing power consumption by non-integer times oversampling
US7069481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2002 |
| Grant date | Jun 27, 2006 |
| Priority date | — |
| Expiry date | Oct 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data recovery circuit has a phase-locked loop for generating a plurality of clock signals; an oversampling unit for non-integer times oversampling serial data, and outputting the oversampled result as sample data formed of a plurality of bits; a pattern detector for receiving the sample data, and generating a pattern signal; a state accumulator for receiving the pattern signal, accumulating the frequency of occurrence of the pattern signal, and outputting the pattern signal having the highest frequency of occurrence as a state signal; a state selector for receiving the state signal, and generating a state selection signal for selecting bits at predetermined positions in the sample data; and a data selector for receiving the sample data, selecting bits of the sample data in response to the state selection signal, and outputting the selected bits as recovered data formed of a plurality of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.