CMOS-TFT Array substrate and method for fabricating the same
US7071036B2 · kind B2 · utility
11Cited by
2References
31Claims
0Family size
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Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Jun 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
Abstract
A TFT array substrate includes a substrate, first–third semiconductor layers, a gate insulating layer, a storage electrode, and a passivation layer. The gate insulating layer separates the first and second semiconductor layers and separates the second and third semiconductor layers. The storage electrode is positioned above the gate insulating layer. A passivation layer encloses the top and side surfaces of the storage electrode. The storage layer and source/drain regions of the first semiconductor layer are doped at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.