Space-saving packaging of electronic circuits
US7071546B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2003 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Jul 17, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53104
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and packaging method for stacking a plurality of integrated circuit substrates, i.e., substrates having integrated circuits formed as integral portions of the substrates, which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantabie device where package volume is at a premium. Furthermore, an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.