Chip-type sensor against ESD and stress damages and contamination interference
US7071708B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Oct 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V40/1329
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chip-type sensor against ESD and stress damages and contamination interference includes a substrate structure and a protection layer covering over the substrate structure. The protection layer includes, from bottom to top, a first layer for providing a first stress against the substrate structure, a second layer for providing a second stress against the substrate structure, and a third layer for providing a third stress against the substrate structure. The first stress and the third stress belong to one of a tensile stress and a compressive stress, and the second stress belongs to the other of the tensile stress and the compressive stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.