Extraction of interconnect parasitics
US7071710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Aug 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.