Apparatus and method for reducing propagation delay
US7071761B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 2004 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Apr 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timer circuit is arranged for reduced propagation delay and improved stability at low supply voltages. The timer circuit includes a capacitor circuit, a voltage offset circuit, an inverter circuit, and a current source circuit. The current source circuit is arranged to provide a current. Also, the capacitor circuit is arranged to provide a voltage ramp in response to the current. The voltage offset circuit is configured to provide a voltage offset. Further, the current source circuit, the capacitor circuit, and the voltage offset current are arranged to provide two voltage ramps that are offset from each other. Additionally, the inverter circuit includes a p-type transistor and an n-type transistor. The p-type transistor is configured to receive one of the two voltage ramps, and the n-type transistor is configured to receive the other of the two voltage ramps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.