Back-drive circuit protection for I/O cells using CMOS process
US7071764B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Jul 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a high tolerance I/O interface with over-voltage protection beyond 5 V, a cascoded driver with PMOS pull-up and NMOS pull-down transistors, connected to a pad, is provided. Circuitry is included to maintain the floating well voltages of the PMOS pull-up driver transistors at substantially the same voltages as their respective drains, and their gate voltages at substantially the same voltages as their respective drains, under back-drive and 5 V tolerant mode. Circuitry is also provided to increase the gate voltage of one of a cascoded pair of NMOS pull-down driver transistors, so that the drain-source junction voltage and gate oxide voltage of the transistor will be less than the breakdown voltage under back-drive and 5 V tolerant mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.