Flexible buffering scheme for multi-rate SIMD processor
US7072357B2 · kind B2 · utility
3Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Mar 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A single instruction, multiple data (SIMD) architecture for controlling the processing of plurality of data streams in a digital subscriber line (DSL) system has a memory for storing the data from the channels, a processor operatively coupled with the memory for processing data from the data streams, and a controller for controlling the processor. Storing the data in the memory de-couples the operating rate of the processor and the operating rate of the data streams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.