Clock timing recovery using arbitrary sampling frequency
US7072431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | Jul 4, 2006 |
| Priority date | — |
| Expiry date | Dec 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0004
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bit timing signal is regenerated from an encoded digital signal in a receiver using a predetermined sample rate Fs. An input pulse signal is generated in response to predetermined transitions of the encoded digital signal. A clock count signal is generated having a variable clock period according to cyclical counting of the clock count signal up to a count value S at the predetermined sample rate, the count value alternating between an upper value Su and a lower value Sl so that the variable clock period has an average length substantially equal to a data bit period of the encoded digital signal. The clock count signal is synchronized with the encoded digital signal by 1) counting the input pulse signals to generate a pulse count, 2) counting sampling periods between successive input pulse signals to generate a sample count, and 3) generating a sync signal if the pulse count is greater than a pulse threshold and the sample count is greater than a sample threshold. The clock count signal and the pulse count are reset in response to the sync signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.