Semiconductor chip package
US7075177B2 · kind B2 · utility
6Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2001 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Oct 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package is formed by a first semiconductor chip and a second semiconductor chip, which have electrodes for wiring at surfaces thereof, being integrated and mounted in a state in which reverse surfaces thereof oppose one another. Therefore, two semiconductor chips can be freely combined and mounted regardless of chip sizes thereof, and lengths of wires can be shortened. Thus, a wire-bonding yield can be improved, and a semiconductor package having excellent electric characteristics can be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.