Semiconductor device
US7075182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2004 |
| Grant date | Jul 11, 2006 |
| Priority date | — |
| Expiry date | Jan 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor device comprises a first conductive pattern 42, a second conductive pattern 42 formed adjacent to the first conductive pattern 42, a first conductor plug 28 formed below a prescribed region of the first conductive pattern 42, a second conductor plug 62n formed over a prescribed region of the first conductive pattern 42, a third conductor plug 28 formed below a prescribed region of the second conductive pattern 42, which is adjacent to a prescribed region of the first conductive pattern 42, a fourth conductor plug 62n+1 formed over a prescribed region of the second conductive pattern 42, a third conductive pattern 64 formed above the first conductive pattern 42 and connected to the second conductor plug 62a, and a fourth conductive pattern 64 formed above the second conductive pattern 42 and connected to the fourth conductor plug 62. The fourth conductor plug 62n+1 is arranged a position which is offset from the second conductor plug 62n. The conductor plugs 62n, 62n+1 are offset each other in the longitudinal direction of the interconnections, whereby the parts of the interconnections having an increased width can be distanced from each other. Thus, the interconne…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.